On 13/09/2024 22:12, Sasha Levin wrote: > > This is a note to let you know that I've just added the patch titled > > riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 > rate to 1.5GHz > > to the 6.10-stable tree which can be found at: > http://www.kernel.org/git/?p=linux/kernel/git/stable/stable- > queue.git;a=summary > > The filename of the patch is: > riscv-dts-starfive-jh7110-common-fix-lower-rate-of-c.patch > and it can be found in the queue-6.10 subdirectory. > > If you, or anyone else, feels it should not be added to the stable tree, please let > <stable@xxxxxxxxxxxxxxx> know about it. > Hi Sasha, This patch only has the part of DTS without the clock driver patch[1]. [1]: https://lore.kernel.org/all/20240826080430.179788-2-xingyu.wu@xxxxxxxxxxxxxxxx/ I don't know your plan about this driver patch, or maybe I missed it. But the DTS changes really needs the driver patch to work and you should add the driver patch. Thanks, Xingyu Wu > > > commit 67b60bf9777bd340c7179adb5376dcdd3f0c260c > Author: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> > Date: Mon Aug 26 16:04:30 2024 +0800 > > riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 > rate to 1.5GHz > > [ Upstream commit 61f2e8a3a94175dbbaad6a54f381b2a505324610 ] > > CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. > But now PLL0 rate is 1GHz and the cpu frequency loads become > 250/333/500/1000MHz in fact. > > The PLL0 rate should be default set to 1.5GHz and set the > cpu_core rate to 500MHz in safe. > > Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") > Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> > Reviewed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > index 68d16717db8c..51d85f447626 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > @@ -354,6 +354,12 @@ spi_dev0: spi@0 { > }; > }; > > +&syscrg { > + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, > + <&pllclk JH7110_PLLCLK_PLL0_OUT>; > + assigned-clock-rates = <500000000>, <1500000000>; }; > + > &sysgpio { > i2c0_pins: i2c0-0 { > i2c-pins {
