Sorry, it was a mistake. You can ignore it. Thank you
On Tue, Sep 10, 2024 at 10:47 PM Ardi Nugraha <0x4rd1@xxxxxxxxx> wrote:
>
> Sorry, it was a mistake. You can ignore it. Thank you
>
> On Tue, 10 Sep 2024 at 22.18 Ardi Nugraha <0x4rd1@xxxxxxxxx> wrote:
>>
>> From: Satya Priya Kakitapalli <quic_skakitap@xxxxxxxxxxx>
>>
>> The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it.
>>
>> Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
>> Cc: stable@xxxxxxxxxxxxxxx
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
>> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@xxxxxxxxxxx>
>> Link: https://lore.kernel.org/r/20240731062916.2680823-2-quic_skakitap@xxxxxxxxxxx
>> Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
>> Signed-off-by: ardinugrxha <0x4rd1@xxxxxxxxx>
>> ---
>> drivers/clk/qcom/clk-alpha-pll.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
>> index d87314042528..9ce45cd6e09f 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -40,7 +40,7 @@
>>
>> #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
>> # define PLL_POST_DIV_SHIFT 8
>> -# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
>> +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
>> # define PLL_ALPHA_EN BIT(24)
>> # define PLL_ALPHA_MODE BIT(25)
>> # define PLL_VCO_SHIFT 20
>> --
>> 2.43.0
>>
