On Sat, Sep 7, 2024 at 5:51 PM Jonathan Cameron <jic23@xxxxxxxxxx> wrote:
>
> On Sat, 7 Sep 2024 09:50:34 +0300
> Alexandru Ardelean <aardelean@xxxxxxxxxxxx> wrote:
>
> > From: Guillaume Stols <gstols@xxxxxxxxxxxx>
> >
> > The current implementation attempts to recover from an eventual glitch
> > in the clock by checking frstdata state after reading the first
> > channel's sample: If frstdata is low, it will reset the chip and
> > return -EIO.
> >
> > This will only work in parallel mode, where frstdata pin is set low
> > after the 2nd sample read starts.
> >
> > For the serial mode, according to the datasheet, "The FRSTDATA output
> > returns to a logic low following the 16th SCLK falling edge.", thus
> > after the Xth pulse, X being the number of bits in a sample, the check
> > will always be true, and the driver will not work at all in serial
> > mode if frstdata(optional) is defined in the devicetree as it will
> > reset the chip, and return -EIO every time read_sample is called.
> >
> > Hence, this check must be removed for serial mode.
> >
> > Fixes: b9618c0cacd7 ("staging: IIO: ADC: New driver for AD7606/AD7606-6/AD7606-4")
> > Signed-off-by: Guillaume Stols <gstols@xxxxxxxxxxxx>
> > Reviewed-by: Nuno Sa <nuno.sa@xxxxxxxxxx>
> > Link: https://patch.msgid.link/20240702-cleanup-ad7606-v3-1-18d5ea18770e@xxxxxxxxxxxx
> > Cc: <Stable@xxxxxxxxxxxxxxx>
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
> Reference the fix patch in your cover letter, but don't include it in the series.
>
> I'll just get confused when I pick this up.
ack
will do
