Thanks.
On 8/31/24 3:41 PM, Krzysztof Kozlowski wrote:
> The property is "fsl,pins", not "fsl,pin". Wrong property means the pin
> configuration was not applied. Fixes dtbs_check warnings:
>
> imx6ull-seeed-npi-dev-board-emmc.dtb: pinctrl@20e0000: uart1grp: 'fsl,pins' is a required property
> imx6ull-seeed-npi-dev-board-emmc.dtb: pinctrl@20e0000: uart1grp: 'fsl,pin' does not match any of the regexes: 'pinctrl-[0-9]+'
>
> Cc: <stable@xxxxxxxxxxxxxxx>
> Fixes: e3b5697195c8 ("ARM: dts: imx6ull: add seeed studio NPi dev board")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Reviewed-by: Parthiban Nallathambi <parthiban@xxxxxxxxxxx>
Thanks,
Parthiban
> ---
> .../dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
> index 6bb12e0bbc7e..50654dbf62e0 100644
> --- a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi
> @@ -339,14 +339,14 @@ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0
> };
>
> pinctrl_uart1: uart1grp {
> - fsl,pin = <
> + fsl,pins = <
> MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
> MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
> >;
> };
>
> pinctrl_uart2: uart2grp {
> - fsl,pin = <
> + fsl,pins = <
> MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
> MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
> MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
> @@ -355,7 +355,7 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
> };
>
> pinctrl_uart3: uart3grp {
> - fsl,pin = <
> + fsl,pins = <
> MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
> MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
> MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
> @@ -364,21 +364,21 @@ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
> };
>
> pinctrl_uart4: uart4grp {
> - fsl,pin = <
> + fsl,pins = <
> MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
> MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
> >;
> };
>
> pinctrl_uart5: uart5grp {
> - fsl,pin = <
> + fsl,pins = <
> MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
> MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
> >;
> };
>
> pinctrl_usb_otg1_id: usbotg1idgrp {
> - fsl,pin = <
> + fsl,pins = <
> MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
> >;
> };
