[PATCH 4.19.y 00/14] arm64: errata: Speculative SSBS workaround

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Hi,

This series is a v4.19-only backport (based on v4.19.319) of the
upstream workaround for SSBS errata on Arm Ltd CPUs, as affected parts
are likely to be used with stable kernels.

The errata mean that an MSR to the SSBS special-purpose register does
not affect subsequent speculative instructions, permitting speculative
store bypassing for a window of time.

The upstream support was original posted as:

* https://lore.kernel.org/linux-arm-kernel/20240508081400.235362-1-mark.rutland@xxxxxxx/
  "arm64: errata: Add workaround for Arm errata 3194386 and 3312417"
  Present in v6.10

* https://lore.kernel.org/linux-arm-kernel/20240603111812.1514101-1-mark.rutland@xxxxxxx/
  "arm64: errata: Expand speculative SSBS workaround"
  Present in v6.11-rc1

* https://lore.kernel.org/linux-arm-kernel/20240801101803.1982459-1-mark.rutland@xxxxxxx/
  "arm64: errata: Expand speculative SSBS workaround (again)"
  Present in v6.11-rc2

This backport applies the patches which are not present in v4.19.y, and
as prerequisites backports the addition of spec_bar() and SB support,
HWCAP detection based on user-visible id register values. and the
addition of Neoverse-V2 MIDR values.

I have tested the backport (when applied to v4.19.319), ensuring that
the detection logic works and that the HWCAP and string in /proc/cpuinfo
are both hidden when the relevant errata are detected.

Mark.

Besar Wicaksono (1):
  arm64: Add Neoverse-V2 part

James Morse (1):
  arm64: cpufeature: Force HWCAP to be based on the sysreg visible to
    user-space

Mark Rutland (11):
  arm64: cputype: Add Cortex-X4 definitions
  arm64: cputype: Add Neoverse-V3 definitions
  arm64: errata: Add workaround for Arm errata 3194386 and 3312417
  arm64: cputype: Add Cortex-X3 definitions
  arm64: cputype: Add Cortex-A720 definitions
  arm64: cputype: Add Cortex-X925 definitions
  arm64: errata: Unify speculative SSBS errata logic
  arm64: errata: Expand speculative SSBS workaround
  arm64: cputype: Add Cortex-X1C definitions
  arm64: cputype: Add Cortex-A725 definitions
  arm64: errata: Expand speculative SSBS workaround (again)

Will Deacon (1):
  arm64: Add support for SB barrier and patch in over DSB; ISB sequences

 Documentation/arm64/silicon-errata.txt | 18 ++++++++
 arch/arm64/Kconfig                     | 38 ++++++++++++++++
 arch/arm64/include/asm/assembler.h     | 13 ++++++
 arch/arm64/include/asm/barrier.h       |  4 ++
 arch/arm64/include/asm/cpucaps.h       |  4 +-
 arch/arm64/include/asm/cputype.h       | 16 +++++++
 arch/arm64/include/asm/sysreg.h        |  6 +++
 arch/arm64/include/asm/uaccess.h       |  3 +-
 arch/arm64/include/uapi/asm/hwcap.h    |  1 +
 arch/arm64/kernel/cpu_errata.c         | 43 ++++++++++++++++++
 arch/arm64/kernel/cpufeature.c         | 61 ++++++++++++++++++++++----
 arch/arm64/kernel/cpuinfo.c            |  1 +
 12 files changed, 197 insertions(+), 11 deletions(-)

-- 
2.30.2





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