Hi, This series is a v6.10-only backport (based on v6.10.3) of the upstream workaround for SSBS errata on Arm Ltd CPUs, as affected parts are likely to be used with stable kernels. This does not apply to earlier stable trees, which will receive a separate backport. The errata mean that an MSR to the SSBS special-purpose register does not affect subsequent speculative instructions, permitting speculative store bypassing for a window of time. The upstream support was original posted as: * https://lore.kernel.org/linux-arm-kernel/20240508081400.235362-1-mark.rutland@xxxxxxx/ "arm64: errata: Add workaround for Arm errata 3194386 and 3312417" Present in v6.10 * https://lore.kernel.org/linux-arm-kernel/20240603111812.1514101-1-mark.rutland@xxxxxxx/ "arm64: errata: Expand speculative SSBS workaround" Present in v6.11-rc1 * https://lore.kernel.org/linux-arm-kernel/20240801101803.1982459-1-mark.rutland@xxxxxxx/ "arm64: errata: Expand speculative SSBS workaround (again)" Present in v6.11-rc2 This backport applies the patches which are not present in v6.10.y. I have tested the backport (when applied to v6.10.3), ensuring that the detection logic works and that the HWCAP and string in /proc/cpuinfo are both hidden when the relevant errata are detected. Mark. Mark Rutland (8): arm64: cputype: Add Cortex-X3 definitions arm64: cputype: Add Cortex-A720 definitions arm64: cputype: Add Cortex-X925 definitions arm64: errata: Unify speculative SSBS errata logic arm64: errata: Expand speculative SSBS workaround arm64: cputype: Add Cortex-X1C definitions arm64: cputype: Add Cortex-A725 definitions arm64: errata: Expand speculative SSBS workaround (again) Documentation/arch/arm64/silicon-errata.rst | 34 ++++++++++- arch/arm64/Kconfig | 62 ++++++++++----------- arch/arm64/include/asm/cpucaps.h | 2 +- arch/arm64/include/asm/cputype.h | 10 ++++ arch/arm64/kernel/cpu_errata.c | 26 ++++++--- arch/arm64/kernel/proton-pack.c | 2 +- 6 files changed, 93 insertions(+), 43 deletions(-) -- 2.30.2
