6.10-stable review patch. If anyone has any objections, please let me know.
------------------
From: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
[ Upstream commit c1380adf2e8680a00dedaf1b25c19beadbbe5bbd ]
The fixed_pll_dco output frequency is not accurate,
add frac factor for fixed_pll_dco clk to fix it.
Fixes: 57b55c76aaf1 ("clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller")
Signed-off-by: Xianwei Zhao <xianwei.zhao@xxxxxxxxxxx>
Link: https://lore.kernel.org/r/20240603-s4_fixedpll-v1-1-2b2a98630841@xxxxxxxxxxx
Signed-off-by: Jerome Brunet <jbrunet@xxxxxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
---
drivers/clk/meson/s4-pll.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
index d2650d96400cf..707c107a52918 100644
--- a/drivers/clk/meson/s4-pll.c
+++ b/drivers/clk/meson/s4-pll.c
@@ -38,6 +38,11 @@ static struct clk_regmap s4_fixed_pll_dco = {
.shift = 0,
.width = 8,
},
+ .frac = {
+ .reg_off = ANACTRL_FIXPLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
.n = {
.reg_off = ANACTRL_FIXPLL_CTRL0,
.shift = 10,
--
2.43.0
