6.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> [ Upstream commit f08407210db921a4c9eaeaa92d0c434858b9c6c4 ] Describe the cache configuration for the first Cortex-A76 CPU core on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Takeshi Kihara. Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@xxxxxxxxx Stable-dep-of: 6fca24a07e1d ("arm64: dts: renesas: r8a779a0: Add missing hypervisor virtual timer IRQ") Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 868d1a3cbdf61..9f6a30cf315f2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -23,6 +23,14 @@ a76_0: cpu@0 { reg = <0>; device_type = "cpu"; power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; + next-level-cache = <&L3_CA76_0>; + }; + + L3_CA76_0: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A779G0_PD_A2E0D0>; + cache-unified; + cache-level = <3>; }; }; -- 2.43.0
