On Tue, Jul 02, 2024 at 09:20:39PM GMT, Satya Priya Kakitapalli wrote:
> The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it.
> Also, correct the pll postdiv shift used in trion pll postdiv
> set rate API. The shift value is not same for different types of
> plls and should be taken from the pll's .post_div_shift member.
Two separate commits for two different fixes, please.
>
> Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@xxxxxxxxxxx>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 8a412ef47e16..6107c144c0f5 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -40,7 +40,7 @@
>
> #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
> # define PLL_POST_DIV_SHIFT 8
> -# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
> +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
> # define PLL_ALPHA_EN BIT(24)
> # define PLL_ALPHA_MODE BIT(25)
> # define PLL_VCO_SHIFT 20
> @@ -1496,8 +1496,8 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
> }
>
> return regmap_update_bits(regmap, PLL_USER_CTL(pll),
> - PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
> - val << PLL_POST_DIV_SHIFT);
> + PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
> + val << pll->post_div_shift);
> }
>
> const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
>
> --
> 2.25.1
>
--
With best wishes
Dmitry
