On Wed, Jun 19, 2024 at 11:26:25AM +0200, Uwe Kleine-König wrote:
> A small prescaler is beneficial, as this improves the resolution of the
> duty_cycle configuration. However if the prescaler is too small, the
> maximal possible period becomes considerably smaller than the requested
> value.
>
> One situation where this goes wrong is the following: With a parent
> clock rate of 208877930 Hz and max_arr = 0xffff = 65535, a request for
> period = 941243 ns currently results in PSC = 1. The value for ARR is
> then calculated to
>
> PSC = 941243 * 208877930 / (1000000000 * 2) - 1 = 98301
^
This ----' must be ARR of course.
> This value is bigger than 65535 however and so doesn't fit into the
> respective register. In this particular case the PWM was configured for
While improving the commit log, I'll do s/register/register field/, too.
> a period of 313733.4806027616 ns (with ARR = 98301 & 0xffff). Even if
> ARR was configured to its maximal value, only period = 627495.6861167669
> ns would be achievable.
Best regards
Uwe
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