[Public]
Reviewed-by: Roman Li <roman.li@xxxxxxx>
> -----Original Message-----
> From: Mahfooz, Hamza <Hamza.Mahfooz@xxxxxxx>
> Sent: Monday, June 3, 2024 10:35 AM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Wentland, Harry <Harry.Wentland@xxxxxxx>; Li, Sun peng (Leo)
> <Sunpeng.Li@xxxxxxx>; Siqueira, Rodrigo <Rodrigo.Siqueira@xxxxxxx>;
> Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Hung, Alex
> <Alex.Hung@xxxxxxx>; Li, Roman <Roman.Li@xxxxxxx>; Mahfooz, Hamza
> <Hamza.Mahfooz@xxxxxxx>; stable@xxxxxxxxxxxxxxx
> Subject: [PATCH] drm/amd/display: prevent register access while in IPS
>
> We can't read/write to DCN registers while in IPS. Since, that can cause the
> system to hang. So, before proceeding with the access in that scenario, force
> the system out of IPS.
>
> Cc: stable@xxxxxxxxxxxxxxx # 6.6+
> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@xxxxxxx>
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10
> ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 059f78c8cd04..c8bc4098ed18 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -11796,6 +11796,12 @@ void amdgpu_dm_trigger_timing_sync(struct
> drm_device *dev)
> mutex_unlock(&adev->dm.dc_lock);
> }
>
> +static inline void amdgpu_dm_exit_ips_for_hw_access(struct dc *dc) {
> + if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)
> + dc_exit_ips_for_hw_access(dc);
> +}
> +
> void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
> u32 value, const char *func_name) { @@ -11806,6
> +11812,8 @@ void dm_write_reg_func(const struct dc_context *ctx, uint32_t
> address,
> return;
> }
> #endif
> +
> + amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
> cgs_write_register(ctx->cgs_device, address, value);
> trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address,
> value); } @@ -11829,6 +11837,8 @@ uint32_t dm_read_reg_func(const
> struct dc_context *ctx, uint32_t address,
> return 0;
> }
>
> + amdgpu_dm_exit_ips_for_hw_access(ctx->dc);
> +
> value = cgs_read_register(ctx->cgs_device, address);
>
> trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address,
> value);
> --
> 2.45.0
