5.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Ikjoon Jang <ikjn@xxxxxxxxxxxx> [ Upstream commit 1781f2c461804c0123f59afc7350e520a88edffb ] mfgcfg clock is under MFG_ASYNC power domain. Fixes: e526c9bc11f8 ("arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile") Fixes: 37fb78b9aeb7 ("arm64: dts: mediatek: Add mt8183 power domains controller") Signed-off-by: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx> Signed-off-by: Ikjoon Jang <ikjn@xxxxxxxxxxxx> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@xxxxxxxxxxxxx> Signed-off-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx> Link: https://lore.kernel.org/r/20240223091122.2430037-1-wenst@xxxxxxxxxxxx Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 97f84aa9fc6e1..1c93f41bc0880 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -577,6 +577,7 @@ compatible = "mediatek,mt8183-mfgcfg", "syscon"; reg = <0 0x13000000 0 0x1000>; #clock-cells = <1>; + power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>; }; mmsys: syscon@14000000 { -- 2.43.0