On Fri, Apr 26, 2024 at 4:59 PM Hugo Villeneuve <hugo@xxxxxxxxxxx> wrote:
>
> From: Hugo Villeneuve <hvilleneuve@xxxxxxxxxxxx>
>
> When using a high speed clock with a low baud rate, the 4x prescaler is
> automatically selected if required. In that case, sc16is7xx_set_baud()
> properly configures the chip registers, but returns an incorrect baud
> rate by not taking into account the prescaler value. This incorrect baud
> rate is then fed to uart_update_timeout().
>
> For example, with an input clock of 80MHz, and a selected baud rate of 50,
> sc16is7xx_set_baud() will return 200 instead of 50.
>
> Fix this by first changing the prescaler variable to hold the selected
> prescaler value instead of the MCR bitfield. Then properly take into
> account the selected prescaler value in the return value computation.
>
> Also add better documentation about the divisor value computation.
>
> Fixes: dfeae619d781 ("serial: sc16is7xx")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Hugo Villeneuve <hvilleneuve@xxxxxxxxxxxx>
> ---
> drivers/tty/serial/sc16is7xx.c | 23 ++++++++++++++++++-----
> 1 file changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
> index 03cf30e20b75..dcd6c5615401 100644
> --- a/drivers/tty/serial/sc16is7xx.c
> +++ b/drivers/tty/serial/sc16is7xx.c
> @@ -555,16 +555,28 @@ static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg)
> return reg == SC16IS7XX_RHR_REG;
> }
>
> +/*
> + * Configure programmable baud rate generator (divisor) according to the
> + * desired baud rate.
> + *
> + * From the datasheet, the divisor is computed according to:
> + *
> + * XTAL1 input frequency
> + * -----------------------
> + * prescaler
> + * divisor = ---------------------------
> + * baud-rate x sampling-rate
> + */
> static int sc16is7xx_set_baud(struct uart_port *port, int baud)
> {
> struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
> u8 lcr;
> - u8 prescaler = 0;
> + int prescaler = 1;
> unsigned long clk = port->uartclk, div = clk / 16 / baud;
>
> if (div >= BIT(16)) {
> - prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
> - div /= 4;
> + prescaler = 4;
> + div /= prescaler;
> }
>
> /* Enable enhanced features */
> @@ -574,9 +586,10 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud)
> SC16IS7XX_EFR_ENABLE_BIT);
> sc16is7xx_efr_unlock(port);
>
> + /* If bit MCR_CLKSEL is set, the divide by 4 prescaler is activated. */
> sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
> SC16IS7XX_MCR_CLKSEL_BIT,
> - prescaler);
> + prescaler == 1 ? 0 : SC16IS7XX_MCR_CLKSEL_BIT);
>
> /* Backup LCR and access special register set (DLL/DLH) */
> lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
> @@ -592,7 +605,7 @@ static int sc16is7xx_set_baud(struct uart_port *port, int baud)
> /* Restore LCR and access to general register set */
> sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
>
> - return DIV_ROUND_CLOSEST(clk / 16, div);
> + return DIV_ROUND_CLOSEST((clk / prescaler) / 16, div);
> }
>
> static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
>
> base-commit: 660a708098569a66a47d0abdad998e29e1259de6
> --
> 2.39.2
>
For me, looks normal. Does not cause problems on my vendored kernel
with my XR20M1172 patches. Do I need to integrate those inside my
patch? Or how should I do?
