On Tue, 2014-12-16 at 18:28 +0800, Zhu Yanjun wrote: > 2.6.x kernels require a similar logic change as commit 6dfaa76 > [e1000e: reset MAC-PHY interconnect on 82577/82578] introduces > for newer kernels. > > During Sx->S0 transitions, the interconnect between the MAC and PHY on > 82577/82578 can remain in SMBus mode instead of transitioning to the > PCIe-like mode required during normal operation. Toggling the > LANPHYPC > Value bit essentially resets the interconnect forcing it to the > correct > mode. > > after review of all intel drivers, found several instances where > drivers had the incorrect pattern of: > memory mapped write(); > delay(); > > which should always be: > memory mapped write(); > write flush(); /* aka memory mapped read */ > delay(); > > explanation: > The reason for including the flush is that writes can be held > (posted) in PCI/PCIe bridges, but the read always has to complete > synchronously and therefore has to flush all pending writes to a > device. If a write is held and followed by a delay, the delay > means nothing because the write may not have reached hardware > (maybe even not until the next read) > > Signed-off-by: Bruce Allan <bruce.w.allan@xxxxxxxxx> > Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@xxxxxxxxx> > Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx> > Signed-off-by: Zhu Yanjun <Yanjun.Zhu@xxxxxxxxxxxxx> > --- > drivers/net/e1000e/defines.h | 2 ++ > drivers/net/e1000e/ich8lan.c | 20 ++++++++++++++++++++ > 2 files changed, 22 insertions(+) To be clear, Zhu is wanting this applied to stable trees (yet did not CC stable@xxxxxxxxxxxxxxx ). Willy- I am fine with this series being applied to stable.
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