On 27-03-24, 08:19, Marcel Ziswiler wrote: > From: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx> > > On the i.MX 8M Mini, the AUX_PLL_REFCLK_SEL has to be left at its reset > default of AUX_IN (PLL clock). > > Background Information: > In our automated testing setup, we use Delock Mini-PCIe SATA cards [1]. > While this setup has proven very stable overall we noticed upstream on > the i.MX 8M Mini fails quite regularly (about 50/50) to bring up the > PCIe link while with NXP's downstream BSP 5.15.71_2.2.2 it always works. > As that old downstream stuff was quite different, I first also tried > NXP's latest downstream BSP 6.1.55_2.2.0 which from a PCIe point of view > is fairly vanilla, however, also there the PCIe link-up was not stable. > Comparing and debugging I noticed that upstream explicitly configures > the AUX_PLL_REFCLK_SEL to I_PLL_REFCLK_FROM_SYSPLL while working > downstream [2] leaving it at reset defaults of AUX_IN (PLL clock). > Unfortunately, the TRM does not mention any further details about this > register (both for the i.MX 8M Mini as well as the Plus). > NXP confirmed their validation codes for the i.MX8MM PCIe doesn't > configure cmn_reg063 (offset: 0x18C). > BTW: On the i.MX 8M Plus we have not seen any issues with PCIe with the > exact same setup which is why I left it unchanged. This does not apply on phy/fixes, pls rebase -- ~Vinod
