On Thu, Dec 11, 2014 at 08:16:59AM +0000, Chris Wilson wrote: > In the gen7 pipe control there is an extra bit to flush the media > caches, so let's set it during cache invalidation flushes. Bspec is telling me this bit is already present in snb, and calls it 'Generic Media State Clear'. Older Bspec seems to suggest we should set it here, and maybe that we should also issue another PIPE_CONTROL with the bit set after MI_SET_CONTEXT when switching from media to 3D context. These notes don't seem to be present in the current BSpec, so I'm not sure what the deal is. > > Cc: Simon Farnsworth <simon@xxxxxxxxxxxx> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Cc: stable@xxxxxxxxxxxxxxx > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 93fdad8a7447..0ddef7256d02 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -400,6 +400,7 @@ > #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) > #define PIPE_CONTROL_CS_STALL (1<<20) > #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) > +#define PIPE_CONTROL_MEDIA_CACHE_INVALIDATE (1<<16) > #define PIPE_CONTROL_QW_WRITE (1<<14) > #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) > #define PIPE_CONTROL_DEPTH_STALL (1<<13) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 4702e7bcd71c..282279b83ca4 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -373,6 +373,7 @@ gen7_render_ring_flush(struct intel_engine_cs *ring, > flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; > flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; > flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; > + flags |= PIPE_CONTROL_MEDIA_CACHE_INVALIDATE; > /* > * TLB invalidate requires a post-sync write. > */ > -- > 2.1.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html