Hi Christian,
ansuelsmth@xxxxxxxxx wrote on Wed, 20 Mar 2024 01:11:39 +0100:
> misc_cmd_type in exec_op have multiple problems. With commit a82990c8a409
> ("mtd: rawnand: qcom: Add read/read_start ops in exec_op path") it was
> reworked and generalized but actually dropped the handling of the
> RESET_DEVICE command.
>
> The rework itself was correct with supporting case where a single misc
> command is handled, but became problematic by the addition of exiting
> early if we didn't had an ERASE or an OP_PROGRAM_PAGE operation.
>
> Also additional logic was added without clear explaination causing the
> erase command to be broken on testing it on a ipq806x nandc.
>
> Add some additional logic to restore RESET_DEVICE command handling and
> fix erase command.
>
> Fixes: a82990c8a409 ("mtd: rawnand: qcom: Add read/read_start ops in exec_op path")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Christian Marangi <ansuelsmth@xxxxxxxxx>
> ---
> drivers/mtd/nand/raw/qcom_nandc.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index b079605c84d3..b8cff9240b28 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -2815,7 +2815,7 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
> host->cfg0_raw & ~(7 << CW_PER_PAGE));
> nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw);
> instrs = 3;
> - } else {
> + } else if (q_op.cmd_reg != OP_RESET_DEVICE) {
> return 0;
> }
>
> @@ -2830,9 +2830,8 @@ static int qcom_misc_cmd_type_exec(struct nand_chip *chip, const struct nand_sub
> nandc_set_reg(chip, NAND_EXEC_CMD, 1);
>
> write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL);
> - (q_op.cmd_reg == OP_BLOCK_ERASE) ? write_reg_dma(nandc, NAND_DEV0_CFG0,
> - 2, NAND_BAM_NEXT_SGL) : read_reg_dma(nandc,
> - NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
> + if (q_op.cmd_reg == OP_BLOCK_ERASE)
> + write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
Ugh. How did that went through...
I don't want to get into the details of this controller, but the fix
looks legitimate.
> write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
> read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
Thanks,
Miquèl
