Hi Alex,
On 2024-02-27 1:48 PM, Alexandre Ghiti wrote:
> Hi Samuel,
>
> On 14/02/2024 10:28, Andrew Jones wrote:
>> On Wed, Feb 14, 2024 at 01:01:56AM -0800, Samuel Holland wrote:
>>> When the kernel is running in M-mode, the CBZE bit must be set in the
>>> menvcfg CSR, not in senvcfg.
>>>
>>> Cc: <stable@xxxxxxxxxxxxxxx>
>>> Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
>>> Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
>>> Signed-off-by: Samuel Holland <samuel.holland@xxxxxxxxxx>
>>> ---
>>>
>>> (no changes since v1)
>>>
>>> arch/riscv/include/asm/csr.h | 2 ++
>>> arch/riscv/kernel/cpufeature.c | 2 +-
>>> 2 files changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
>>> index 510014051f5d..2468c55933cd 100644
>>> --- a/arch/riscv/include/asm/csr.h
>>> +++ b/arch/riscv/include/asm/csr.h
>>> @@ -424,6 +424,7 @@
>>> # define CSR_STATUS CSR_MSTATUS
>>> # define CSR_IE CSR_MIE
>>> # define CSR_TVEC CSR_MTVEC
>>> +# define CSR_ENVCFG CSR_MENVCFG
>>> # define CSR_SCRATCH CSR_MSCRATCH
>>> # define CSR_EPC CSR_MEPC
>>> # define CSR_CAUSE CSR_MCAUSE
>>> @@ -448,6 +449,7 @@
>>> # define CSR_STATUS CSR_SSTATUS
>>> # define CSR_IE CSR_SIE
>>> # define CSR_TVEC CSR_STVEC
>>> +# define CSR_ENVCFG CSR_SENVCFG
>>> # define CSR_SCRATCH CSR_SSCRATCH
>>> # define CSR_EPC CSR_SEPC
>>> # define CSR_CAUSE CSR_SCAUSE
>>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
>>> index 89920f84d0a3..c5b13f7dd482 100644
>>> --- a/arch/riscv/kernel/cpufeature.c
>>> +++ b/arch/riscv/kernel/cpufeature.c
>>> @@ -950,7 +950,7 @@ arch_initcall(check_unaligned_access_all_cpus);
>>> void riscv_user_isa_enable(void)
>>> {
>>> if (riscv_cpu_has_extension_unlikely(smp_processor_id(),
>>> RISCV_ISA_EXT_ZICBOZ))
>>> - csr_set(CSR_SENVCFG, ENVCFG_CBZE);
>>> + csr_set(CSR_ENVCFG, ENVCFG_CBZE);
>>> }
>>> #ifdef CONFIG_RISCV_ALTERNATIVE
>>> --
>>> 2.43.0
>>>
>> After our back and forth on how we determine the existence of the *envcfg
>> CSRs, I wonder if we shouldn't put a comment above this
>> riscv_user_isa_enable() function capturing the [current] decision.
>>
>> Something like
>>
>> /*
>> * While the [ms]envcfg CSRs weren't defined until priv spec 1.12,
>> * they're assumed to be present when an extension is present which
>> * specifies [ms]envcfg bit(s). Hence, we don't do any additional
>> * priv spec version checks or CSR probes here.
>> */
>
>
> I was about to read the whole discussion in v2 to understand the v3...thank you
> Drew :) I think it really makes sense to add this comment, do you intend to do
> so Samuel?
Yes, I am about to send a v4 with the changes from the previous discussion,
including a RISCV_ISA_EXT_XLINUXENVCFG bit specifically for the presence of the
[ms]envcfg CSR and a comment like the above.
Regards,
Samuel
