6.6-stable review patch. If anyone has any objections, please let me know.
------------------
From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
[ Upstream commit 45e8c72712345263208f7c94f334fa718634f557 ]
The PCIe controllers on 8180 are cache-coherent. Mark them as such.
Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances")
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20231219-topic-8180_pcie_dmac-v1-1-5d00fc1b23fd@xxxxxxxxxx
Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 486f7ffef43b..0d85bdec5a82 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -1751,6 +1751,7 @@ pcie0: pci@1c00000 {
phys = <&pcie0_lane>;
phy-names = "pciephy";
+ dma-coherent;
status = "disabled";
};
@@ -1858,6 +1859,7 @@ pcie3: pci@1c08000 {
phys = <&pcie3_lane>;
phy-names = "pciephy";
+ dma-coherent;
status = "disabled";
};
@@ -1965,6 +1967,7 @@ pcie1: pci@1c10000 {
phys = <&pcie1_lane>;
phy-names = "pciephy";
+ dma-coherent;
status = "disabled";
};
@@ -2072,6 +2075,7 @@ pcie2: pci@1c18000 {
phys = <&pcie2_lane>;
phy-names = "pciephy";
+ dma-coherent;
status = "disabled";
};
--
2.43.0
