6.5-stable review patch. If anyone has any objections, please let me know.
------------------
From: Jisheng Zhang <jszhang@xxxxxxxxxx>
[ Upstream commit 759426c758c7053a941a4c06c7571461439fcff6 ]
riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't
dma coherent, so set dma-noncoherent to reflect this fact.
Signed-off-by: Jisheng Zhang <jszhang@xxxxxxxxxx>
Tested-by: Drew Fustini <dfustini@xxxxxxxxxxxx>
Reviewed-by: Guo Ren <guoren@xxxxxxxxxx>
Signed-off-by: Arnd Bergmann <arnd@xxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 56a73134b49e6..58108f0eb3fdc 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -139,6 +139,7 @@
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
+ dma-noncoherent;
ranges;
plic: interrupt-controller@ffd8000000 {
--
2.42.0
