On 27/10/2023 01.22, Mark Brown wrote: > On Thu, Oct 26, 2023 at 04:49:19PM +0100, Mark Brown wrote: >> When we sync the register cache we do so with the cache bypassed in order >> to avoid overhead from writing the synced values back into the cache. If >> the regmap has ranges and the selector register for those ranges is in a >> register which is cached this has the unfortunate side effect of meaning >> that the physical and cached copies of the selector register can be out of >> sync after a cache sync. The cache will have whatever the selector was when >> the sync started and the hardware will have the selector for the register >> that was synced last. > > Given the nearness to the release I've dropped this into my CI and am > intending to just apply it as soon as that's done in the hopes that it > hits tomorrow's -next and gets a bit more coverage, it would be great if > you could confirm if this fixes the systems where you saw the original > issue. Can confirm, this fixes the sleep borking issue on my end after reverting my workaround. Tested-by: Hector Martin <marcan@xxxxxxxxx> - Hector
