5.10-stable review patch. If anyone has any objections, please let me know.
------------------
From: Dikshita Agarwal <dikshita@xxxxxxxxxxxxxx>
[ Upstream commit 7f6631295f46070ee5cdbe939136ce48cc617272 ]
- Add X2 RPMh registers and definitions from the downstream example.
- Add 6xx core power definitions
- Add 6xx AON definitions
- Add 6xx wrapper tz definitions
- Add 6xx wrapper interrupt definitions
- Add 6xx soft interrupt definitions
- Define wrapper LPI register offsets
Signed-off-by: Dikshita Agarwal <dikshita@xxxxxxxxxxxxxx>
Co-developed-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@xxxxxxxxxx>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx>
Stable-dep-of: d74e48160980 ("media: venus: hfi_venus: Write to VIDC_CTRL_INIT after unmasking interrupts")
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
---
.../media/platform/qcom/venus/hfi_venus_io.h | 30 +++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/media/platform/qcom/venus/hfi_venus_io.h b/drivers/media/platform/qcom/venus/hfi_venus_io.h
index 4c392b67252c2..9cad15eac9e80 100644
--- a/drivers/media/platform/qcom/venus/hfi_venus_io.h
+++ b/drivers/media/platform/qcom/venus/hfi_venus_io.h
@@ -53,10 +53,22 @@
#define UC_REGION_ADDR 0x64
#define UC_REGION_SIZE 0x68
+#define CPU_CS_H2XSOFTINTEN_V6 0x148
+
+#define CPU_CS_X2RPMH_V6 0x168
+#define CPU_CS_X2RPMH_MASK0_BMSK_V6 0x1
+#define CPU_CS_X2RPMH_MASK0_SHFT_V6 0x0
+#define CPU_CS_X2RPMH_MASK1_BMSK_V6 0x2
+#define CPU_CS_X2RPMH_MASK1_SHFT_V6 0x1
+#define CPU_CS_X2RPMH_SWOVERRIDE_BMSK_V6 0x4
+#define CPU_CS_X2RPMH_SWOVERRIDE_SHFT_V6 0x3
+
/* Relative to CPU_IC_BASE */
#define CPU_IC_SOFTINT 0x18
+#define CPU_IC_SOFTINT_V6 0x150
#define CPU_IC_SOFTINT_H2A_MASK 0x8000
#define CPU_IC_SOFTINT_H2A_SHIFT 0xf
+#define CPU_IC_SOFTINT_H2A_SHIFT_V6 0x0
/* Venus wrapper */
#define WRAPPER_BASE 0x000e0000
@@ -84,6 +96,9 @@
#define WRAPPER_INTR_MASK_A2HCPU_MASK 0x4
#define WRAPPER_INTR_MASK_A2HCPU_SHIFT 0x2
+#define WRAPPER_INTR_STATUS_A2HWD_MASK_V6 0x8
+#define WRAPPER_INTR_MASK_A2HWD_BASK_V6 0x8
+
#define WRAPPER_INTR_CLEAR 0x14
#define WRAPPER_INTR_CLEAR_A2HWD_MASK 0x10
#define WRAPPER_INTR_CLEAR_A2HWD_SHIFT 0x4
@@ -93,6 +108,8 @@
#define WRAPPER_POWER_STATUS 0x44
#define WRAPPER_VDEC_VCODEC_POWER_CONTROL 0x48
#define WRAPPER_VENC_VCODEC_POWER_CONTROL 0x4c
+#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_V6 0x54
+#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS_V6 0x58
#define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET 0x64
#define WRAPPER_CPU_CLOCK_CONFIG 0x2000
@@ -121,4 +138,17 @@
#define WRAPPER_VCODEC1_MMCC_POWER_STATUS 0x110
#define WRAPPER_VCODEC1_MMCC_POWER_CONTROL 0x114
+/* Venus 6xx */
+#define WRAPPER_CORE_POWER_STATUS_V6 0x80
+#define WRAPPER_CORE_POWER_CONTROL_V6 0x84
+
+/* Wrapper TZ 6xx */
+#define WRAPPER_TZ_BASE_V6 0x000c0000
+#define WRAPPER_TZ_CPU_STATUS_V6 0x10
+
+/* Venus AON */
+#define AON_BASE_V6 0x000e0000
+#define AON_WRAPPER_MVP_NOC_LPI_CONTROL 0x00
+#define AON_WRAPPER_MVP_NOC_LPI_STATUS 0x04
+
#endif
--
2.40.1
