This is a note to let you know that I've just added the patch titled
ARM: dts: zynq: Enable PL clocks for Parallella
to the 3.17-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm-dts-zynq-enable-pl-clocks-for-parallella.patch
and it can be found in the queue-3.17 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@xxxxxxx>
Date: Thu, 6 Nov 2014 18:22:10 +0100
Subject: ARM: dts: zynq: Enable PL clocks for Parallella
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From: =?UTF-8?q?Andreas=20F=C3=A4rber?= <afaerber@xxxxxxx>
commit 92c9e0c780e61f821ab8a08f0d4d4fd33ba1197c upstream.
The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.
Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
Signed-off-by: Andreas Färber <afaerber@xxxxxxx>
Acked-by: Michal Simek <michal.simek@xxxxxxxxxx>
Signed-off-by: Olof Johansson <olof@xxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/arm/boot/dts/zynq-parallella.dts | 4 ++++
1 file changed, 4 insertions(+)
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
};
};
+&clkc {
+ fclk-enable = <0xf>;
+};
+
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
Patches currently in stable-queue which might be from afaerber@xxxxxxx are
queue-3.17/arm-dts-zynq-enable-pl-clocks-for-parallella.patch
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