Hi Greg,
These patches are backported to make LPAE more robust, most of which
are important bugfixs. So I suggest merging them into 3.10.
For ARM, when LPAE is triggered, 40-bit physical address is available,
translation table becomes 3-level, and every table entry is 64 bit
instead of 32. However, 3.10 does not well adapt to the change, So
comes this series of patches.
There are 12 patches, 9 of which can be cherry-picked cleanly, the
rest needs to be adjusted. Patch information as follows:
PART 1: patches that can be cleanly applied:
dde1b65 ARM: mm: correct pte_same behaviour for LPAE.
926edcc ARM: LPAE: use signed arithmetic for mask definitions
20d6956 ARM: LPAE: use phys_addr_t in alloc_init_pud()
5b20c5b ARM: fix type of PHYS_PFN_OFFSET to unsigned long
e38a517 ARM: lpae: fix definition of PTE_HWTABLE_PTRS
237f123 ARM: 7866/1: include: asm: use 'long long' instead of
'u64' within atomic.h
4dcc1cf ARM: 7867/1: include: asm: use 'int' instead of
'unsigned long' for 'oldval' in atomic_cmpxchg().
efea340 ARM: 7931/1: Correct virt_addr_valid
6b07699 ARM: DMA: ensure that old section mappings are flushed
from the TLB
PART 2: patches that should be adjusted:
b713aa0 ARM: fix asm/memory.h build error
f295070 ARM: 8108/1: mm: Introduce {pte,pmd}_isset and
{pte,pmd}_isclear
ded9477 ARM: 8109/1: mm: Modify pte_write and pmd_write
logic for LPAE
Thanks!
arch/arm/include/asm/atomic.h | 52 +++++++++++++++--------------
arch/arm/include/asm/memory.h | 36 ++++++++++----------
arch/arm/include/asm/page.h | 2 +-
arch/arm/include/asm/pgtable-3level-hwdef.h | 1 +
arch/arm/include/asm/pgtable-3level.h | 31 +++++++++++++----
arch/arm/include/asm/pgtable.h | 14 +++++---
arch/arm/kernel/head.S | 2 +-
arch/arm/mm/dma-mapping.c | 11 +++++-
arch/arm/mm/mmu.c | 3 +-
arch/arm/mm/proc-v7-3level.S | 9 +++--
10 files changed, 100 insertions(+), 61 deletions(-)
--
1.8.3.4
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