6.5-stable review patch. If anyone has any objections, please let me know.
------------------
From: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
commit 37cfd5e457cbdcd030f378127ff2d62776f641e7 upstream.
The PLL14xx hardware can be found on i.MX8M{M,N,P} SoCs and always come
with a 6-bit pre-divider. Neither the reference manuals nor the
datasheets of these SoCs do mention any restrictions. Furthermore the
current code doesn't respect the restrictions from the comment too.
Therefore drop the restriction and align the max pre-divider (pdiv)
value to 63 to get more accurate frequencies.
Fixes: b09c68dc57c9 ("clk: imx: pll14xx: Support dynamic rates")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Marco Felsch <m.felsch@xxxxxxxxxxxxxx>
Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
Reviewed-by: Adam Ford <aford173@xxxxxxxxx>
Signed-off-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>
Acked-by: Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>
Tested-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
Link: https://lore.kernel.org/r/20230807084744.1184791-1-m.felsch@xxxxxxxxxxxxxx
Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/clk/imx/clk-pll14xx.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
--- a/drivers/clk/imx/clk-pll14xx.c
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -137,11 +137,10 @@ static void imx_pll14xx_calc_settings(st
/*
* Fractional PLL constrains:
*
- * a) 6MHz <= prate <= 25MHz
- * b) 1 <= p <= 63 (1 <= p <= 4 prate = 24MHz)
- * c) 64 <= m <= 1023
- * d) 0 <= s <= 6
- * e) -32768 <= k <= 32767
+ * a) 1 <= p <= 63
+ * b) 64 <= m <= 1023
+ * c) 0 <= s <= 6
+ * d) -32768 <= k <= 32767
*
* fvco = (m * 65536 + k) * prate / (p * 65536)
*/
@@ -184,7 +183,7 @@ static void imx_pll14xx_calc_settings(st
}
/* Finally calculate best values */
- for (pdiv = 1; pdiv <= 7; pdiv++) {
+ for (pdiv = 1; pdiv <= 63; pdiv++) {
for (sdiv = 0; sdiv <= 6; sdiv++) {
/* calc mdiv = round(rate * pdiv * 2^sdiv) / prate) */
mdiv = DIV_ROUND_CLOSEST(rate * (pdiv << sdiv), prate);
