The patch below does not apply to the 5.15-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable@xxxxxxxxxxxxxxx>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-5.15.y git checkout FETCH_HEAD git cherry-pick -x 1e611e104b9acb6310b8c684d5acee0e11ca7bd1 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable@xxxxxxxxxxxxxxx>' --in-reply-to '2023091600-powdered-lanky-892a@gregkh' --subject-prefix 'PATCH 5.15.y' HEAD^.. Possible dependencies: 1e611e104b9a ("mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT") d534fd9787d5 ("mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR") 4095f4d9225a ("mtd: spi-nor: Fix divide by zero for spi-nor-generic flashes") df6def86b9dc ("mtd: spi-nor: spansion: Add support for s25hl02gt and s25hs02gt") 91f3c430f622 ("mtd: spi-nor: spansion: Add a new ->ready() hook for multi-chip device") 6c01ae11130c ("mtd: spi-nor: spansion: Rework cypress_nor_get_page_size() for multi-chip device support") e570f7872a34 ("mtd: spi-nor: Allow post_sfdp hook to return errors") 120c94a67b26 ("mtd: spi-nor: spansion: Rename method to cypress_nor_get_page_size") a9180c298d35 ("mtd: spi-nor: spansion: Enable JFFS2 write buffer for S25FS256T") 4199c1719e24 ("mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s25hx SEMPER flash") 9fd0945fe6fa ("mtd: spi-nor: spansion: Enable JFFS2 write buffer for Infineon s28hx SEMPER flash") c87c9b11c53c ("mtd: spi-nor: spansion: Determine current address mode") 4e53ab0c292d ("mtd: spi-nor: Set the 4-Byte Address Mode method based on SFDP data") d75c22f376f6 ("mtd: spi-nor: core: Update name and description of spi_nor_set_4byte_addr_mode") f1f1976224f3 ("mtd: spi-nor: core: Update name and description of spansion_set_4byte_addr_mode") 288df4378319 ("mtd: spi-nor: core: Update name and description of micron_st_nor_set_4byte_addr_mode") 076aa4eac8b3 ("mtd: spi-nor: core: Move generic method to core - micron_st_nor_set_4byte_addr_mode") 79a4db50192c ("mtd: spi-nor: Delay the initialization of bank_size") 4eddee70140b ("mtd: spi-nor: Add a RWW flag") 6afcc84080c4 ("mtd: spi-nor: spansion: Add support for Infineon S25FS256T") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From 1e611e104b9acb6310b8c684d5acee0e11ca7bd1 Mon Sep 17 00:00:00 2001 From: Takahiro Kuwano <Takahiro.Kuwano@xxxxxxxxxxxx> Date: Wed, 26 Jul 2023 10:52:48 +0300 Subject: [PATCH] mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT CFR2V[7] is assigned to Flash's address mode (3- or 4-ybte) and must not be changed when writing MEMLAT (CFR2V[3:0]). CFR2V shall be used in a read, update, write back fashion. Fixes: c3266af101f2 ("mtd: spi-nor: spansion: add support for Cypress Semper flash") Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@xxxxxxxxxxxx> Cc: stable@xxxxxxxxxxxxxxx Link: https://lore.kernel.org/r/20230726075257.12985-3-tudor.ambarus@xxxxxxxxxx Signed-off-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxx> diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 6b2532ed053c..6460d2247bdf 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -4,6 +4,7 @@ * Copyright (C) 2014, Freescale Semiconductor, Inc. */ +#include <linux/bitfield.h> #include <linux/device.h> #include <linux/mtd/spi-nor.h> @@ -28,6 +29,7 @@ #define SPINOR_REG_CYPRESS_CFR2 0x3 #define SPINOR_REG_CYPRESS_CFR2V \ (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR2) +#define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0) #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7) #define SPINOR_REG_CYPRESS_CFR3 0x4 @@ -161,8 +163,18 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor) int ret; u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; + op = (struct spi_mem_op) + CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, + SPINOR_REG_CYPRESS_CFR2V, 0, buf); + + ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); + if (ret) + return ret; + /* Use 24 dummy cycles for memory array reads. */ - *buf = SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24; + *buf &= ~SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK; + *buf |= FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK, + SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24); op = (struct spi_mem_op) CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, SPINOR_REG_CYPRESS_CFR2V, 1, buf);
