6.1-stable review patch. If anyone has any objections, please let me know.
------------------
From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
[ Upstream commit 4390730cc12af25f7c997f477795f5f4200149c0 ]
The Kryo names (once again) turned out to be fake. The CPUs report:
0x412fd050 (CA55 r2p0) (0 - 3)
0x411fd410 (CA78 r1p1) (4 - 6)
0x411fd440 (CX1 r1p1) (7)
Use the compatibles that reflect that.
Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20230706-topic-sm8350-cpu-compat-v1-1-f8d6a1869781@xxxxxxxxxx
Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 0b5a1841d607d..b3245b13b2611 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -63,7 +63,7 @@ cpus {
CPU0: cpu@0 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
@@ -82,7 +82,7 @@ L3_0: l3-cache {
CPU1: cpu@100 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
@@ -98,7 +98,7 @@ L2_100: l2-cache {
CPU2: cpu@200 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
@@ -114,7 +114,7 @@ L2_200: l2-cache {
CPU3: cpu@300 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
@@ -130,7 +130,7 @@ L2_300: l2-cache {
CPU4: cpu@400 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a78";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
@@ -146,7 +146,7 @@ L2_400: l2-cache {
CPU5: cpu@500 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a78";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
@@ -163,7 +163,7 @@ L2_500: l2-cache {
CPU6: cpu@600 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-a78";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
@@ -179,7 +179,7 @@ L2_600: l2-cache {
CPU7: cpu@700 {
device_type = "cpu";
- compatible = "qcom,kryo685";
+ compatible = "arm,cortex-x1";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
--
2.40.1
