From: Ladislav Michl <ladis@xxxxxxxxxxxxxx> [ Upstream commit fb57f829beefd4b3746f1b23d51e80ed5d4bb87b ] Although valid USB clock divider will be calculated for all valid Octeon core frequencies, make code formally correct limiting divider not to be greater that 7 so it fits into H_CLKDIV_SEL field. Signed-off-by: Ladislav Michl <ladis@xxxxxxxxxxxxxx> Reported-by: Linux Kernel Functional Testing <lkft@xxxxxxxxxx> Closes: https://qa-reports.linaro.org/lkft/linux-next-master/build/next-20230808/testrun/18882876/suite/build/test/gcc-8-cavium_octeon_defconfig/log Acked-by: Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx> Link: https://lore.kernel.org/r/ZNIM7tlBNdHFzXZG@lenoch Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> --- arch/mips/cavium-octeon/octeon-usb.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index 2add435ad0387..165e032d08647 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -243,11 +243,11 @@ static int dwc3_octeon_get_divider(void) while (div < ARRAY_SIZE(clk_div)) { uint64_t rate = octeon_get_io_clock_rate() / clk_div[div]; if (rate <= 300000000 && rate >= 150000000) - break; + return div; div++; } - return div; + return -EINVAL; } static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) @@ -374,6 +374,10 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) /* Step 4b: Select controller clock frequency. */ div = dwc3_octeon_get_divider(); + if (div < 0) { + dev_err(dev, "clock divider invalid\n"); + return div; + } val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div); -- 2.40.1
