On 11/06/2014 06:22 PM, Andreas Färber wrote: > The Parallella board comes with a U-Boot bootloader that loads one of > two predefined FPGA bitstreams before booting the kernel. Both define an > AXI interface to the on-board Epiphany processor. > > Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. > > Otherwise accessing, e.g., the ESYSRESET register freezes the board, > as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. > > Cc: <stable@xxxxxxxxxxxxxxx> # 3.17.x > Signed-off-by: Andreas Färber <afaerber@xxxxxxx> > --- > Michal/Olof, please consider this trivial patch as a fix for 3.18. Acked-by: Michal Simek <michal.simek@xxxxxxxxxx> Olof, Arnd: Can you please pick this directly? Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html