6.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Srinivas Goud <srinivas.goud@xxxxxxx> commit 627d05a41ca1fbb9d390f9513af262f001f261f7 upstream. Remove 10us delay in cdns_spi_process_fifo() (called from cdns_spi_irq()) to fix data corruption issue on Master side when this driver configured in Slave mode, as Slave is failed to prepare the date on time due to above delay. Add 10us delay before processing the RX FIFO as TX empty doesn't guarantee valid data in RX FIFO. Signed-off-by: Srinivas Goud <srinivas.goud@xxxxxxx> Reviewed-by: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx> Tested-by: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxx> Link: https://lore.kernel.org/r/1692610216-217644-1-git-send-email-srinivas.goud@xxxxxxx Signed-off-by: Mark Brown <broonie@xxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/spi/spi-cadence.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) --- a/drivers/spi/spi-cadence.c +++ b/drivers/spi/spi-cadence.c @@ -316,12 +316,6 @@ static void cdns_spi_process_fifo(struct xspi->rx_bytes -= nrx; while (ntx || nrx) { - /* When xspi in busy condition, bytes may send failed, - * then spi control did't work thoroughly, add one byte delay - */ - if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL) - udelay(10); - if (ntx) { if (xspi->txbuf) cdns_spi_write(xspi, CDNS_SPI_TXD, *xspi->txbuf++); @@ -391,6 +385,11 @@ static irqreturn_t cdns_spi_irq(int irq, if (xspi->tx_bytes) { cdns_spi_process_fifo(xspi, trans_cnt, trans_cnt); } else { + /* Fixed delay due to controller limitation with + * RX_NEMPTY incorrect status + * Xilinx AR:65885 contains more details + */ + udelay(10); cdns_spi_process_fifo(xspi, 0, trans_cnt); cdns_spi_write(xspi, CDNS_SPI_IDR, CDNS_SPI_IXR_DEFAULT); @@ -438,12 +437,18 @@ static int cdns_transfer_one(struct spi_ cdns_spi_setup_transfer(spi, transfer); } else { /* Set TX empty threshold to half of FIFO depth - * only if TX bytes are more than half FIFO depth. + * only if TX bytes are more than FIFO depth. */ if (xspi->tx_bytes > xspi->tx_fifo_depth) cdns_spi_write(xspi, CDNS_SPI_THLD, xspi->tx_fifo_depth >> 1); } + /* When xspi in busy condition, bytes may send failed, + * then spi control didn't work thoroughly, add one byte delay + */ + if (cdns_spi_read(xspi, CDNS_SPI_ISR) & CDNS_SPI_IXR_TXFULL) + udelay(10); + cdns_spi_process_fifo(xspi, xspi->tx_fifo_depth, 0); spi_transfer_delay_exec(transfer);
