On Mon, 2023-07-17 at 17:07 +0800, walter.chang@xxxxxxxxxxxx wrote:
> From: Walter Chang <walter.chang@xxxxxxxxxxxx>
>
> Due to the fact that the use of `writeq_relaxed()` to program CVAL is
> not guaranteed to be atomic, it is necessary to disable the timer
> before
> programming CVAL.
>
> However, if the MMIO timer is already enabled and has not yet
> expired,
> there is a possibility of unexpected behavior occurring: when the CPU
> enters the idle state during this period, and if the CPU's local
> event
> is earlier than the broadcast event, the following process occurs:
>
> tick_broadcast_enter()
> tick_broadcast_oneshot_control(TICK_BROADCAST_ENTER)
> __tick_broadcast_oneshot_control()
> ___tick_broadcast_oneshot_control()
> tick_broadcast_set_event()
> clockevents_program_event()
> set_next_event_mem()
>
> During this process, the MMIO timer remains enabled while programming
> CVAL. To prevent such behavior, disable timer explicitly prior to
> programming CVAL.
>
> Fixes: 8b82c4f883a7 ("clocksource/drivers/arm_arch_timer: Move MMIO
> timer programming over to CVAL")
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Walter Chang <walter.chang@xxxxxxxxxxxx>
> ---
> drivers/clocksource/arm_arch_timer.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/clocksource/arm_arch_timer.c
> b/drivers/clocksource/arm_arch_timer.c
> index e733a2a1927a..7dd2c615bce2 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -792,6 +792,13 @@ static __always_inline void
> set_next_event_mem(const int access, unsigned long e
> u64 cnt;
>
> ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
> +
> + /* Timer must be disabled before programming CVAL */
> + if (ctrl & ARCH_TIMER_CTRL_ENABLE) {
> + ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
> + arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl,
> clk);
> + }
> +
> ctrl |= ARCH_TIMER_CTRL_ENABLE;
> ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
>
Gentle ping for this patch.
Thanks,
Walter Chang
