Re: [PATCH V5] PCI: qcom: Fixing broken pcie enumeration for 2_3_3 configs ops

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On 24. 07. 2023. 08:34, Sricharan Ramabadhran wrote:
PARF_SLV_ADDR_SPACE_SIZE_2_3_3 macro is used for IPQ8074 2_3_3 post_init.
PCIe slave addr register offset is 0x358, but was wrongly changed to
0x168 as a part of commit 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix
from register definitions"). Fixing it, by using the right macro and remove
the unused PARF_SLV_ADDR_SPACE_SIZE_2_3_3.

Without this access to the registers of slave addr space like iATU etc
are broken leading to pcie enumeration failure.

Fixes: 39171b33f652 ("PCI: qcom: Remove PCIE20_ prefix from register definitions")
Cc: <Stable@xxxxxxxxxxxxxxx>
Reviewed-by: Manivannan Sadhasivam <mani@xxxxxxxxxx>
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@xxxxxxxxxxx>

I can confirm this fixes Gen2 PCIe on Xiaomi AX9000 (IPQ8072A) so:
Tested-by: Robert Marko <robimarko@xxxxxxxxx>

---
  [v5] Fixed subject, commit log
  [v4] Fix commit sub and added '<mani@xxxxxxxxxx>' reviewed-by tag
  [v3] Added reviewed-by tag, fixed subject, commit text
  [v2] Fixed the 'fixes tag' correctly, subject, right macro usage

  drivers/pci/controller/dwc/pcie-qcom.c | 4 +---
  1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4ab30892f6ef..8418894b3de7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -43,7 +43,6 @@
  #define PARF_PHY_REFCLK				0x4c
  #define PARF_CONFIG_BITS			0x50
  #define PARF_DBI_BASE_ADDR			0x168
-#define PARF_SLV_ADDR_SPACE_SIZE_2_3_3		0x16c /* Register offset specific to IP ver 2.3.3 */
  #define PARF_MHI_CLOCK_RESET_CTRL		0x174
  #define PARF_AXI_MSTR_WR_ADDR_HALT		0x178
  #define PARF_AXI_MSTR_WR_ADDR_HALT_V2		0x1a8
@@ -810,8 +809,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
  	u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
  	u32 val;
- writel(SLV_ADDR_SPACE_SZ,
-		pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3);
+	writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
val = readl(pcie->parf + PARF_PHY_CTRL);
  	val &= ~PHY_TEST_PWR_DOWN;




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