Hi Andrzej, > > diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > index 7566c89d9def3..9d050b9a19194 100644 > > --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c > > @@ -218,6 +218,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) > > bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; > > + /* > > + * When required, in MTL+ platforms we need to > > + * set the CCS_FLUSH bit in the pipe control > > + */ > > + if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70)) > > + bit_group_0 |= PIPE_CONTROL_CCS_FLUSH; > > + > > > Btw, not for this patch, but related: rcs and ccs have slightly different > set of flushes according to bspec but this functions is the same for both. > Is it sth we should address, or just safe simplification. I guess this is not only used for ccs aux invalidation. I think the BSPEC is specifying the minimum set of bits that need to be set in the pipe control. So that I left it as it is and just added this bit for MTL+. Thanks, Andi
