The patch below does not apply to the 4.14-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable@xxxxxxxxxxxxxxx>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-4.14.y git checkout FETCH_HEAD git cherry-pick -x a33d700e8eea76c62120cb3dbf5e01328f18319a # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable@xxxxxxxxxxxxxxx>' --in-reply-to '2023072143-slam-trickery-68af@gregkh' --subject-prefix 'PATCH 4.14.y' HEAD^.. Possible dependencies: a33d700e8eea ("PCI: qcom: Disable write access to read only registers for IP v2.3.3") 6e0832fa432e ("PCI: Collect all native drivers under drivers/pci/controller/") e52d38f4abf4 ("Merge branch 'lorenzo/pci/rockchip'") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From a33d700e8eea76c62120cb3dbf5e01328f18319a Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam <mani@xxxxxxxxxx> Date: Mon, 19 Jun 2023 20:34:00 +0530 Subject: [PATCH] PCI: qcom: Disable write access to read only registers for IP v2.3.3 In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. Link: https://lore.kernel.org/r/20230619150408.8468-2-manivannan.sadhasivam@xxxxxxxxxx Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> Signed-off-by: Lorenzo Pieralisi <lpieralisi@xxxxxxxxxx> Cc: <stable@xxxxxxxxxxxxxxx> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 4ab30892f6ef..ef385d36d653 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -836,6 +836,8 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); + dw_pcie_dbi_ro_wr_dis(pci); + return 0; }
