From: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx> [ Upstream commit 9d498cce9298a71e3896e2d1aee24a1a4c531d81 ] Add the cpufreq nodes for MT8192 SoC. Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx> Tested-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx> Tested-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> Link: https://lore.kernel.org/r/20230317061944.15434-1-allen-kh.cheng@xxxxxxxxxxxx Signed-off-by: Matthias Brugger <matthias.bgg@xxxxxxxxx> Stable-dep-of: a4366b5695c9 ("arm64: dts: mediatek: mt8192: Fix CPUs capacity-dmips-mhz") Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 87b91c8feaf96..ba49f37933d6d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -70,6 +70,7 @@ cpu0: cpu@0 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; capacity-dmips-mhz = <530>; }; @@ -87,6 +88,7 @@ cpu1: cpu@100 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; capacity-dmips-mhz = <530>; }; @@ -104,6 +106,7 @@ cpu2: cpu@200 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; capacity-dmips-mhz = <530>; }; @@ -121,6 +124,7 @@ cpu3: cpu@300 { d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&l2_0>; + performance-domains = <&performance 0>; capacity-dmips-mhz = <530>; }; @@ -138,6 +142,7 @@ cpu4: cpu@400 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -155,6 +160,7 @@ cpu5: cpu@500 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -172,6 +178,7 @@ cpu6: cpu@600 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -189,6 +196,7 @@ cpu7: cpu@700 { d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&l2_1>; + performance-domains = <&performance 1>; capacity-dmips-mhz = <1024>; }; @@ -318,6 +326,12 @@ soc { compatible = "simple-bus"; ranges; + performance: performance-controller@11bc10 { + compatible = "mediatek,cpufreq-hw"; + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; + #performance-domain-cells = <1>; + }; + gic: interrupt-controller@c000000 { compatible = "arm,gic-v3"; #interrupt-cells = <4>; -- 2.39.2
