This is a note to let you know that I've just added the patch titled
sparc64: Define VA hole at run time, rather than at compile time.
to the 3.17-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
sparc64-define-va-hole-at-run-time-rather-than-at-compile-time.patch
and it can be found in the queue-3.17 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From foo@baz Tue Oct 28 11:21:07 CST 2014
From: "David S. Miller" <davem@xxxxxxxxxxxxx>
Date: Fri, 26 Sep 2014 21:58:33 -0700
Subject: sparc64: Define VA hole at run time, rather than at compile time.
From: "David S. Miller" <davem@xxxxxxxxxxxxx>
[ Upstream commit 4397bed080598001e88f612deb8b080bb1cc2322 ]
Now that we use 4-level page tables, we can provide up to 53-bits of
virtual address space to the user.
Adjust the VA hole based upon the capabilities of the cpu type probed.
Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx>
Acked-by: Bob Picco <bob.picco@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/sparc/include/asm/page_64.h | 15 ++++-----------
arch/sparc/mm/init_64.c | 21 +++++++++++++++++++++
2 files changed, 25 insertions(+), 11 deletions(-)
--- a/arch/sparc/include/asm/page_64.h
+++ b/arch/sparc/include/asm/page_64.h
@@ -102,21 +102,14 @@ typedef unsigned long pgprot_t;
typedef pte_t *pgtable_t;
-/* These two values define the virtual address space range in which we
- * must forbid 64-bit user processes from making mappings. It used to
- * represent precisely the virtual address space hole present in most
- * early sparc64 chips including UltraSPARC-I. But now it also is
- * further constrained by the limits of our page tables, which is
- * 43-bits of virtual address.
- */
-#define SPARC64_VA_HOLE_TOP _AC(0xfffffc0000000000,UL)
-#define SPARC64_VA_HOLE_BOTTOM _AC(0x0000040000000000,UL)
+extern unsigned long sparc64_va_hole_top;
+extern unsigned long sparc64_va_hole_bottom;
/* The next two defines specify the actual exclusion region we
* enforce, wherein we use a 4GB red zone on each side of the VA hole.
*/
-#define VA_EXCLUDE_START (SPARC64_VA_HOLE_BOTTOM - (1UL << 32UL))
-#define VA_EXCLUDE_END (SPARC64_VA_HOLE_TOP + (1UL << 32UL))
+#define VA_EXCLUDE_START (sparc64_va_hole_bottom - (1UL << 32UL))
+#define VA_EXCLUDE_END (sparc64_va_hole_top + (1UL << 32UL))
#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \
_AC(0x0000000070000000,UL) : \
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -1630,25 +1630,46 @@ static void __init page_offset_shift_pat
}
}
+unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
+unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
+
static void __init setup_page_offset(void)
{
unsigned long max_phys_bits = 40;
if (tlb_type == cheetah || tlb_type == cheetah_plus) {
+ /* Cheetah/Panther support a full 64-bit virtual
+ * address, so we can use all that our page tables
+ * support.
+ */
+ sparc64_va_hole_top = 0xfff0000000000000UL;
+ sparc64_va_hole_bottom = 0x0010000000000000UL;
+
max_phys_bits = 42;
} else if (tlb_type == hypervisor) {
switch (sun4v_chip_type) {
case SUN4V_CHIP_NIAGARA1:
case SUN4V_CHIP_NIAGARA2:
+ /* T1 and T2 support 48-bit virtual addresses. */
+ sparc64_va_hole_top = 0xffff800000000000UL;
+ sparc64_va_hole_bottom = 0x0000800000000000UL;
+
max_phys_bits = 39;
break;
case SUN4V_CHIP_NIAGARA3:
+ /* T3 supports 48-bit virtual addresses. */
+ sparc64_va_hole_top = 0xffff800000000000UL;
+ sparc64_va_hole_bottom = 0x0000800000000000UL;
+
max_phys_bits = 43;
break;
case SUN4V_CHIP_NIAGARA4:
case SUN4V_CHIP_NIAGARA5:
case SUN4V_CHIP_SPARC64X:
default:
+ /* T4 and later support 52-bit virtual addresses. */
+ sparc64_va_hole_top = 0xfff8000000000000UL;
+ sparc64_va_hole_bottom = 0x0008000000000000UL;
max_phys_bits = 47;
break;
}
Patches currently in stable-queue which might be from davem@xxxxxxxxxxxxx are
queue-3.17/sparc64-adjust-vmalloc-region-size-based-upon-available-virtual-address-bits.patch
queue-3.17/sparc64-fix-fpu-register-corruption-with-aes-crypto-offload.patch
queue-3.17/sparc64-move-request_irq-from-ldc_bind-to-ldc_alloc.patch
queue-3.17/sparc32-dma_alloc_coherent-must-honour-gfp-flags.patch
queue-3.17/sparc64-kill-unnecessary-tables-and-increase-max_banks.patch
queue-3.17/sparc-let-memset-return-the-address-argument.patch
queue-3.17/sparc64-use-kernel-page-tables-for-vmemmap.patch
queue-3.17/sparc64-sparse-irq.patch
queue-3.17/sparc64-fix-physical-memory-management-regressions-with-large-max_phys_bits.patch
queue-3.17/sparc64-fix-lockdep-warnings-on-reboot-on-ultra-5.patch
queue-3.17/sparc64-switch-to-4-level-page-tables.patch
queue-3.17/sparc64-sun4v-tlb-error-power-off-events.patch
queue-3.17/sparc64-increase-size-of-boot-string-to-1024-bytes.patch
queue-3.17/sparc64-find_node-adjustment.patch
queue-3.17/sparc64-fix-reversed-start-end-in-flush_tlb_kernel_range.patch
queue-3.17/sparc64-increase-max_phys_address_bits-to-53.patch
queue-3.17/sparc64-define-va-hole-at-run-time-rather-than-at-compile-time.patch
queue-3.17/sparc64-fix-register-corruption-in-top-most-kernel-stack-frame-during-boot.patch
queue-3.17/sparc64-support-m6-and-m7-for-building-cpu-distribution-map.patch
queue-3.17/sparc64-cpu-hardware-caps-support-for-sparc-m6-and-m7.patch
queue-3.17/sparc64-do-not-define-thread-fpregs-save-area-as-zero-length-array.patch
queue-3.17/sparc64-t5-pmu.patch
queue-3.17/sparc64-adjust-ktsb-assembler-to-support-larger-physical-addresses.patch
queue-3.17/sparc64-implement-__get_user_pages_fast.patch
queue-3.17/sparc64-fix-corrupted-thread-fault-code.patch
queue-3.17/sparc64-fix-hibernation-code-refrence-to-page_offset.patch
queue-3.17/sparc64-correctly-recognise-m6-and-m7-cpu-type.patch
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