On Fri, Jun 09, 2023 at 10:01:02PM +0000, Oliver Upton wrote: > AmpereOne has an erratum in its implementation of FEAT_HAFDBS that > required disabling the feature on the design. This was done by reporting > the feature as not implemented in the ID register, although the > corresponding control bits were not actually RES0. This does not align > well with the requirements of the architecture, which mandates these > bits be RES0 if HAFDBS isn't implemented. > > The kernel's use of stage-1 is unaffected, as the HA and HD bits are > only set if HAFDBS is detected in the ID register. KVM, on the other > hand, relies on the RES0 behavior at stage-2 to use the same value for > VTCR_EL2 on any cpu in the system. Mitigate the non-RES0 behavior by > leaving VTCR_EL2.HA clear on affected systems. > > Cc: stable@xxxxxxxxxxxxxxx > Cc: D Scott Phillips <scott@xxxxxxxxxxxxxxxxxxxxxx> > Cc: Darren Hart <darren@xxxxxxxxxxxxxxxxxxxxxx> > Signed-off-by: Oliver Upton <oliver.upton@xxxxxxxxx> For the non-KVM bits in here: Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx>
