On Fri, May 26, 2023 at 05:18:34PM -0700, Daniel Sneddon wrote: > From: Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx> > > The INVLPG instruction is used to invalidate TLB entries for a > specified virtual address. When PCIDs are enabled, INVLPG is supposed > to invalidate TLB entries for the specified address for both the > current PCID *and* Global entries. (Note: Only kernel mappings set > Global=1.) > > Unfortunately, some INVLPG implementations can leave Global > translations unflushed when PCIDs are enabled. > > As a workaround, never enable PCIDs on affected processors. > > I expect there to eventually be microcode mitigations to replace this > software workaround. However, the exact version numbers where that > will happen are not known today. Once the version numbers are set in > stone, the processor list can be tweaked to only disable PCIDs on > affected processors with affected microcode. > > Note: if anyone wants a quick fix that doesn't require patching, just > stick 'nopcid' on your kernel command-line. > > Signed-off-by: Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx> > Reviewed-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx> > Cc: stable@xxxxxxxxxxxxxxx > (cherry picked from commit ce0b15d11ad837fbacc5356941712218e38a0a83) > Signed-off-by: Daniel Sneddon <daniel.sneddon@xxxxxxxxxxxxxxx> > --- > arch/x86/include/asm/intel-family.h | 5 +++++ > arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ > 2 files changed, 30 insertions(+) All now queued up, thanks. greg k-h
