The patch below does not apply to the 6.3-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable@xxxxxxxxxxxxxxx>. To reproduce the conflict and resubmit, you may use the following commands: git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.3.y git checkout FETCH_HEAD git cherry-pick -x 825b3772a2047bd32ed3b3914234da0de19ef2e0 # <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<stable@xxxxxxxxxxxxxxx>' --in-reply-to '2023051333-matcher-chihuahua-80da@gregkh' --subject-prefix 'PATCH 6.3.y' HEAD^.. Possible dependencies: 825b3772a204 ("drm/amd/display: Do not set DRR on pipe Commit") 36951fc9460f ("Revert "drm/amd/display: Do not set DRR on pipe commit"") thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From 825b3772a2047bd32ed3b3914234da0de19ef2e0 Mon Sep 17 00:00:00 2001 From: Wesley Chalmers <Wesley.Chalmers@xxxxxxx> Date: Thu, 3 Nov 2022 22:29:31 -0400 Subject: [PATCH] drm/amd/display: Do not set DRR on pipe Commit [WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. Cc: stable@xxxxxxxxxxxxxxx Cc: Mario Limonciello <mario.limonciello@xxxxxxx> Reviewed-by: Jun Lei <Jun.Lei@xxxxxxx> Acked-by: Qingqing Zhuo <qingqing.zhuo@xxxxxxx> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@xxxxxxx> Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c index 586de81fc2da..6d328b7e07a8 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c @@ -990,8 +990,5 @@ void dcn30_prepare_bandwidth(struct dc *dc, dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz); dcn20_prepare_bandwidth(dc, context); - - dc_dmub_srv_p_state_delegate(dc, - context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching, context); }
