From: Yang Yingliang <yangyingliang@xxxxxxxxxx> commit 73e770f085023da327dc9ffeb6cd96b0bb22d97e upstream. Add missing free_irq() before return error from sifive_l2_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@xxxxxxxxxx> Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> [conor: ccache -> l2_cache] Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> --- drivers/soc/sifive/sifive_l2_cache.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c index 483aeaf0d405..1248127009f6 100644 --- a/drivers/soc/sifive/sifive_l2_cache.c +++ b/drivers/soc/sifive/sifive_l2_cache.c @@ -221,7 +221,7 @@ static int __init sifive_l2_init(void) rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL); if (rc) { pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]); - goto err_unmap; + goto err_free_irq; } } @@ -235,6 +235,9 @@ static int __init sifive_l2_init(void) #endif return 0; +err_free_irq: + while (--i >= 0) + free_irq(g_irq[i], NULL); err_unmap: iounmap(l2_base); return rc; -- 2.39.2