From: Sean Christopherson <seanjc@xxxxxxxxxx> commit ab52be1b310bcb39e6745d34a8f0e8475d67381a upstream. Reject attempts to set bits 63:32 for 32-bit x2APIC registers, i.e. all x2APIC registers except ICR. Per Intel's SDM: Non-zero writes (by WRMSR instruction) to reserved bits to these registers will raise a general protection fault exception Opportunistically fix a typo in a nearby comment. Reported-by: Marc Orr <marcorr@xxxxxxxxxx> Cc: stable@xxxxxxxxxxxxxxx Reviewed-by: Maxim Levitsky <mlevitsk@xxxxxxxxxx> Link: https://lore.kernel.org/r/20230107011025.565472-3-seanjc@xxxxxxxxxx Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx> [Alejandro: stable backport 5.15.y] Mainline commit: 5429478d038f ("KVM: x86: Add helpers to handle 64-bit APIC MSR read/writes") introduces helper kvm_lapic_msr_write(). Apply the changes to the call sites of the helper in kvm_x2apic_msr_write() and kvm_hv_vapic_msr_write() instead. Signed-off-by: Alejandro Jimenez <alejandro.j.jimenez@xxxxxxxxxx> --- Sanity tested by booting Linux guest on Intel Skylake-SP host (enable_apicv=Y). arch/x86/kvm/lapic.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 8c9e41ff2a24..243aa43f7113 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2802,6 +2802,10 @@ int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) /* if this is ICR write vector before command */ if (reg == APIC_ICR) kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); + else if (data >> 32) + /* Bits 63:32 are reserved in all other registers. */ + return 1; + return kvm_lapic_reg_write(apic, reg, (u32)data); } @@ -2836,6 +2840,10 @@ int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) /* if this is ICR write vector before command */ if (reg == APIC_ICR) kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); + else if (data >> 32) + /* Bits 63:32 are reserved in all other registers. */ + return 1; + return kvm_lapic_reg_write(apic, reg, (u32)data); } -- 2.34.2
