Hi Sasha, sashal@xxxxxxxxxx wrote on Sat, 4 Mar 2023 22:50:38 -0500: > This is a note to let you know that I've just added the patch titled > > mtd: rawnand: fsl_elbc: Propagate HW ECC settings to HW > > to the 5.4-stable tree which can be found at: > http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary > > The filename of the patch is: > mtd-rawnand-fsl_elbc-propagate-hw-ecc-settings-to-hw.patch > and it can be found in the queue-5.4 subdirectory. > > If you, or anyone else, feels it should not be added to the stable tree, > please let <stable@xxxxxxxxxxxxxxx> know about it. +Marek As reported by kernel test robot, this commit does not apply on 5.4 because many changes have happened in the core since the introduction of the fixed patch. In practice the driver works in most cases, but does not in few rare cases (IIUC) so I would be in favor of just dropping this commit from the queue/5.4 branch. If someone feels like this commit should be backported there, please send an updated fix. Link: https://lore.kernel.org/oe-kbuild-all/202303060514.1ziBICF7-lkp@xxxxxxxxx/ Thanks, Miquèl > > > > commit 839c09472742b383f65eb7c1f7e576ebfb6a1f62 > Author: Pali Rohár <pali@xxxxxxxxxx> > Date: Sat Jan 28 14:41:11 2023 +0100 > > mtd: rawnand: fsl_elbc: Propagate HW ECC settings to HW > > [ Upstream commit b56265257d38af5abf43bd5461ca166b401c35a5 ] > > It is possible that current chip->ecc.engine_type value does not match to > configured HW value (if HW ECC checking and generating is enabled or not). > > This can happen with old U-Boot bootloader version which either does not > initialize NAND (and let it in some default unusable state) or initialize > NAND with different parameters than what is specified in kernel DTS file. > > So if kernel chose to use some chip->ecc.engine_type settings (e.g. from > DTS file) then do not depend on bootloader HW configuration and configures > HW ECC settings according to chip->ecc.engine_type value. > > BR_DECC must be set to BR_DECC_CHK_GEN when HW is doing ECC (both > generating and checking), or to BR_DECC_OFF when HW is not doing ECC. > > This change fixes usage of SW ECC support in case bootloader explicitly > enabled HW ECC support and kernel DTS file has specified to use SW ECC. > (Of course this works only in case when NAND is not a boot device and both > bootloader and kernel are loaded from different location, e.g. FLASH NOR.) > > Fixes: f6424c22aa36 ("mtd: rawnand: fsl_elbc: Make SW ECC work") > Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> > Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx> > Link: https://lore.kernel.org/linux-mtd/20230128134111.32559-1-pali@xxxxxxxxxx > Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> > > diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c > index 634c550db13a7..e900c0eddc21d 100644 > --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c > +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c > @@ -727,6 +727,7 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip) > struct fsl_lbc_ctrl *ctrl = priv->ctrl; > struct fsl_lbc_regs __iomem *lbc = ctrl->regs; > unsigned int al; > + u32 br; > > switch (chip->ecc.mode) { > /* > @@ -762,6 +763,13 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip) > return -EINVAL; > } > > + /* enable/disable HW ECC checking and generating based on if HW ECC was chosen */ > + br = in_be32(&lbc->bank[priv->bank].br) & ~BR_DECC; > + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) > + out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_CHK_GEN); > + else > + out_be32(&lbc->bank[priv->bank].br, br | BR_DECC_OFF); > + > /* calculate FMR Address Length field */ > al = 0; > if (chip->pagemask & 0xffff0000)
