From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
[ Upstream commit 01b6041454e8bc4f5feb76e6bcdc83a48cea21f2 ]
In its current form, UFS did not even probe successfully - it failed
when trying to set XO (ref_clk) to 300 MHz instead of doing so to
the ICE clk. Moreover, the missing reg-names prevented ICE from
working or being discovered at all. Fix both of these issues.
As a sidenote, the log reveals that this SoC uses UFS ICE v3.1.0.
Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi")
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Reviewed-by: Iskren Chernev <me@xxxxxxxxxxx>
Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20221208201401.530555-1-konrad.dybcio@xxxxxxxxxx
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 572bf04adf906..3f4017bc667d6 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -704,6 +704,7 @@ opp-202000000 {
ufs_mem_hc: ufs@4804000 {
compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
+ reg-names = "std", "ice";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
@@ -736,10 +737,10 @@ ufs_mem_hc: ufs@4804000 {
<0 0>,
<0 0>,
<37500000 150000000>,
- <75000000 300000000>,
<0 0>,
<0 0>,
- <0 0>;
+ <0 0>,
+ <75000000 300000000>;
status = "disabled";
};
--
2.39.2
