On Tue, Mar 07, 2023 at 05:00:25PM +0100, gregkh@xxxxxxxxxxxxxxxxxxx wrote: > > The patch below does not apply to the 6.2-stable tree. > If someone wants it applied there, or to any other stable or longterm > tree, then please email the backport, including the original git commit > id to <stable@xxxxxxxxxxxxxxx>. This shouldn't be backported as Zbb support was a v6.3 feature. > > To reproduce the conflict and resubmit, you may use the following commands: > > git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.2.y > git checkout FETCH_HEAD > git cherry-pick -x 1eac28201ac0725192f5ced34192d281a06692e5 > # <resolve conflicts, build, test, etc.> > git commit -s > git send-email --to '<stable@xxxxxxxxxxxxxxx>' --in-reply-to '167820482516243@xxxxxxxxx' --subject-prefix 'PATCH 6.2.y' HEAD^.. > > Possible dependencies: > > 1eac28201ac0 ("RISC-V: fix ordering of Zbb extension") > 80c200b34ee8 ("RISC-V: resort all extensions in consistent orders") > > thanks, > > greg k-h > > ------------------ original commit in Linus's tree ------------------ > > >From 1eac28201ac0725192f5ced34192d281a06692e5 Mon Sep 17 00:00:00 2001 > From: Heiko Stuebner <heiko.stuebner@xxxxxxxx> > Date: Wed, 8 Feb 2023 23:53:27 +0100 > Subject: [PATCH] RISC-V: fix ordering of Zbb extension > > As Andrew reported, > Zb* comes after Zi* according 27.11 "Subset Naming Convention" > so fix the ordering accordingly. > > Reported-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx> > Signed-off-by: Heiko Stuebner <heiko.stuebner@xxxxxxxx> > Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx> > Tested-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > Link: https://lore.kernel.org/r/20230208225328.1636017-2-heiko@xxxxxxxxx > Cc: stable@xxxxxxxxxxxxxxx > Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx> > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 420228e219f7..8400f0cc9704 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -185,9 +185,9 @@ arch_initcall(riscv_cpuinfo_init); > * New entries to this struct should follow the ordering rules described above. > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > - __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), >
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