Davidlohr Bueso wrote: > On Mon, 06 Feb 2023, Gregory Price wrote: > > >On Sun, Feb 05, 2023 at 05:02:29PM -0800, Dan Williams wrote: > >> Summary: > >> -------- > >> > >> CXL RAM support allows for the dynamic provisioning of new CXL RAM > >> regions, and more routinely, assembling a region from an existing > >> configuration established by platform-firmware. The latter is motivated > >> by CXL memory RAS (Reliability, Availability and Serviceability) > >> support, that requires associating device events with System Physical > >> Address ranges and vice versa. > >> > >> The 'Soft Reserved' policy rework arranges for performance > >> differentiated memory like CXL attached DRAM, or high-bandwidth memory, > >> to be designated for 'System RAM' by default, rather than the device-dax > >> dedicated access mode. That current device-dax default is confusing and > >> surprising for the Pareto of users that do not expect memory to be > >> quarantined for dedicated access by default. Most users expect all > >> 'System RAM'-capable memory to show up in FREE(1). > > > >Leverage the same QEMU branch, machine, and configuration as my prior > >tests, i'm now experiencing a kernel panic on boot. Will debug a bit > >in the morning, but here is the stack trace i'm seeing > > > >Saw this in both 1 and 2 root port configurations > > I also see it in "regular" pmem setups, and narrowed it down to this > change in the last patch: > > -module_init(cxl_acpi_init); > +/* load before dax_hmem sees 'Soft Reserved' CXL ranges */ > +subsys_initcall(cxl_acpi_init); Yeah, I need to add some CONFIG_CXL_ACPI=y and CONFIG_CXL_BUS=y configs to my tests. Typically I only run module builds.
