On Wed, Oct 5, 2022 at 3:03 PM Suraj Jitindar Singh <surajjs@xxxxxxxxxx> wrote: > > tl;dr: The existing mitigation for eIBRS PBRSB predictions uses an INT3 to > ensure a call instruction retires before a following unbalanced RET. Replace > this with a WRMSR serialising instruction which has a lower performance > penalty. The INT3 is only on a speculative path and should not impact performance. > == Background == > > eIBRS (enhanced indirect branch restricted speculation) is used to prevent > predictor addresses from one privilege domain from being used for prediction > in a higher privilege domain. > > == Problem == > > On processors with eIBRS protections there can be a case where upon VM exit > a guest address may be used as an RSB prediction for an unbalanced RET if a > CALL instruction hasn't yet been retired. This is termed PBRSB (Post-Barrier > Return Stack Buffer). > > A mitigation for this was introduced in: > (2b1299322016731d56807aa49254a5ea3080b6b3 x86/speculation: Add RSB VM Exit protections) > > This mitigation [1] has a ~1% performance impact on VM exit compared to without > it [2]. > > == Solution == > > The WRMSR instruction can be used as a speculation barrier and a serialising > instruction. Use this on the VM exit path instead to ensure that a CALL > instruction (in this case the call to vmx_spec_ctrl_restore_host) has retired > before the prediction of a following unbalanced RET. I don't buy this solution. According to https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/advisory-guidance/post-barrier-return-stack-buffer-predictions.html: "Note that a WRMSR instruction (used to set IBRS, for example), could also serve as a speculation barrier for such a sequence in place of LFENCE." This says only that you can replace the LFENCE with a WRMSR. It doesn't say that you can drop the rest of the sequence. > This mitigation [3] has a negligible performance impact. > > == Testing == > > Run the outl_to_kernel kvm-unit-tests test 200 times per configuration which > counts the cycles for an exit to kernel mode. > > [1] With existing mitigation: > Average: 2026 cycles > [2] With no mitigation: > Average: 2008 cycles > [3] With proposed mitigation: > Average: 2008 cycles What testing did you do to see that this is an effective mitigation? Improved timings are irrelevant if it doesn't work.
