On Wed, Aug 31, 2022 at 09:27:25PM +0800, Lucas Wei wrote: > From: James Morse <james.morse@xxxxxxx> > > commit 39fdb65f52e9a53d32a6ba719f96669fd300ae78 upstream. > > Cortex-A510 is affected by an erratum where in rare circumstances the > CPUs may not handle a race between a break-before-make sequence on one > CPU, and another CPU accessing the same page. This could allow a store > to a page that has been unmapped. > > Work around this by adding the affected CPUs to the list that needs > TLB sequences to be done twice. > > Cc: stable@xxxxxxxxxxxxxxx # 5.15.x > Signed-off-by: James Morse <james.morse@xxxxxxx> > Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@xxxxxxx > Signed-off-by: Will Deacon <will@xxxxxxxxxx> > Signed-off-by: Lucas Wei <lucaswei@xxxxxxxxxx> > --- > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 17 +++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 8 +++++++- > 3 files changed, 26 insertions(+), 1 deletion(-) Now queued up, thanks. greg k-h
