On Tue, Aug 30, 2022 at 11:08:04PM +0800, Lucas Wei wrote: > From: James Morse <james.morse@xxxxxxx> > > Cortex-A510 is affected by an erratum where in rare circumstances the > CPUs may not handle a race between a break-before-make sequence on one > CPU, and another CPU accessing the same page. This could allow a store > to a page that has been unmapped. > > Work around this by adding the affected CPUs to the list that needs > TLB sequences to be done twice. > > Signed-off-by: James Morse <james.morse@xxxxxxx> > Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@xxxxxxx > Signed-off-by: Will Deacon <will@xxxxxxxxxx> > --- > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 17 +++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 8 +++++++- > 3 files changed, 26 insertions(+), 1 deletion(-) What is the upstream commit id of this patch in Linus's tree, and what tree(s) do you want it applied to? Always be specific, remember, some of us have to deal with over a thousand emails a day... thanks, greg k-h
