Hi Greg,
For v5.19, I can cherry-pick this patch directly from commit
39fdb65f52e9 ("arm64:
errata: Add Cortex-A510 to the repeat tlbi list") to linux-5.19.y
without conflicts.
For v5.15, below is my working backport based on linux-5.15.y.
Please let me know if anything can be refined or needs to be changed.
Thanks for your help and review!
----
>From d4722275e4d7b686dc79363159e141b71f62f7d4 Mon Sep 17 00:00:00 2001
From: James Morse <james.morse@xxxxxxx>
Date: Mon, 4 Jul 2022 16:57:32 +0100
Subject: [PATCH] arm64: errata: Add Cortex-A510 to the repeat tlbi list
Cortex-A510 is affected by an erratum where in rare circumstances the
CPUs may not handle a race between a break-before-make sequence on one
CPU, and another CPU accessing the same page. This could allow a store
to a page that has been unmapped.
Work around this by adding the affected CPUs to the list that needs
TLB sequences to be done twice.
Signed-off-by: James Morse <james.morse@xxxxxxx>
Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@xxxxxxx
Signed-off-by: Will Deacon <will@xxxxxxxxxx>
Signed-off-by: Lucas Wei <lucaswei@xxxxxxxxxx>
---
Documentation/arm64/silicon-errata.rst | 2 ++
arch/arm64/Kconfig | 17 +++++++++++++++++
arch/arm64/kernel/cpu_errata.c | 8 +++++++-
3 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/arm64/silicon-errata.rst
b/Documentation/arm64/silicon-errata.rst
index 7c1750bcc5bd..46644736e583 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -92,6 +92,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A77 | #1508412 |
ARM64_ERRATUM_1508412 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A510 | #2441009 |
ARM64_ERRATUM_2441009 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #1188873,1418040|
ARM64_ERRATUM_1418040 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #1349291 | N/A
|
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 69e7e293f72e..9d80c783142f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -666,6 +666,23 @@ config ARM64_ERRATUM_1508412
If unsure, say Y.
+config ARM64_ERRATUM_2441009
+ bool "Cortex-A510: Completion of affected memory accesses might not
be guaranteed by completion of a TLBI"
+ default y
+ select ARM64_WORKAROUND_REPEAT_TLBI
+ help
+ This option adds a workaround for ARM Cortex-A510 erratum #2441009.
+
+ Under very rare circumstances, affected Cortex-A510 CPUs
+ may not handle a race between a break-before-make sequence on one
+ CPU, and another CPU accessing the same page. This could allow a
+ store to a page that has been unmapped.
+
+ Work around this by adding the affected CPUs to the list that needs
+ TLB sequences to be done twice.
+
+ If unsure, say Y.
+
config CAVIUM_ERRATUM_22375
bool "Cavium erratum 22375, 24313"
default y
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index c67c19d70159..e1be45fc7f5b 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -211,6 +211,12 @@ static const struct arm64_cpu_capabilities
arm64_repeat_tlbi_list[] = {
/* Kryo4xx Gold (rcpe to rfpe) => (r0p0 to r3p0) */
ERRATA_MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xe),
},
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_2441009
+ {
+ /* Cortex-A510 r0p0 -> r1p1. Fixed in r1p2 */
+ ERRATA_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
+ },
#endif
{},
};
@@ -427,7 +433,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
#endif
#ifdef CONFIG_ARM64_WORKAROUND_REPEAT_TLBI
{
- .desc = "Qualcomm erratum 1009, or ARM erratum 1286807",
+ .desc = "Qualcomm erratum 1009, or ARM erratum 1286807, 2441009",
.capability = ARM64_WORKAROUND_REPEAT_TLBI,
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
.matches = cpucap_multi_entry_cap_matches,
--
On Tue, Aug 30, 2022 at 1:57 PM Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx> wrote:
>
> On Tue, Aug 30, 2022 at 10:31:35AM +0800, Lucas Wei wrote:
> > Dear Linux stable kernel maintainers,
> >
> > I would like to apply the below patch into kernel v5.15-stable.
> > - subject:arm64: errata: Add Cortex-A510 to the repeat tlbi list
> > - Upstream Commit ID: 39fdb65f52e9a53d32a6ba719f96669fd300ae78
> > - Targeted LTS release: v5.15
> >
> > This patch is an errata of #2441009. Since v5.15 is still in its LTS
> > lifecycle, I think it fits the rule of "New device IDs and quirks are
> > also accepted" and I want to request to apply this patch to kernel
> > v5.15.
>
> You also need it in 5.19.y, right? And you never want someone to
> upgrade from an older kernel to a newer one and have a regression.
>
> This commit does not cleanly cherry-pick, I need a working backport in
> order to apply it. As I'm sure you already have a working and tested
> backport of it (otherwise you wouldn't have asked for it), can you
> please send it to us so that it can be applied?
>
> Same for 5.19.y too.
>
> thanks,
>
> greg k-h
--
Lucas Wei
Embedded Software Engineer
lucaswei@xxxxxxxxxx
0287260408
