From: Pali Roh�<pali@xxxxxxxxxx> commit 0fc75d87454195885bd1a81fc7e6ce92572b6109 upstream. Currently enabling PCI_EXP_RTSTA_PME bit in PCI_EXP_RTCTL register does nothing. This is because PCIe PME driver expects to receive PCIe interrupt defined in PCI_EXP_FLAGS_IRQ register, but aardvark hardware does not trigger PCIe INTx/MSI interrupt for PME event, rather it triggers custom aardvark interrupt which this driver is not processing yet. Fix this issue by handling PME interrupt in advk_pcie_handle_int() and chaining it to PCIe interrupt 0 with generic_handle_domain_irq() (since aardvark sets PCI_EXP_FLAGS_IRQ to zero). With this change PCIe PME driver finally starts receiving PME interrupt. Link: https://lore.kernel.org/r/20220110015018.26359-17-kabel@xxxxxxxxxx Signed-off-by: Pali Roh�<pali@xxxxxxxxxx> Signed-off-by: Marek Beh�abel@xxxxxxxxxx> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> Signed-off-by: Marek Beh�abel@xxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/pci/controller/pci-aardvark.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -1478,6 +1478,18 @@ static void advk_pcie_handle_int(struct isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK); + /* Process PME interrupt */ + if (isr0_status & PCIE_MSG_PM_PME_MASK) { + /* + * Do not clear PME interrupt bit in ISR0, it is cleared by IRQ + * receiver by writing to the PCI_EXP_RTSTA register of emulated + * root bridge. Aardvark HW returns zero for PCI_EXP_FLAGS_IRQ, + * so use PCIe interrupt 0. + */ + if (generic_handle_domain_irq(pcie->irq_domain, 0) == -EINVAL) + dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n"); + } + /* Process ERR interrupt */ if (isr0_status & PCIE_ISR0_ERR_MASK) { advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);
